I’ve been working on a new PCB, and I feel its far enough in development to let you know about it.
It’s a Smart USB Thumb Drive, implemented on two-layer PCB that I’m building into a comprehensive KiCad course, recorded from scratch on the upcoming KiCad 10 release (I will post separately about KiCad 10).
This is a real-world, production-grade design with genuine engineering trade-offs, signal integrity challenges, and lot’s of learning involved.
Here’s a quick summary of the board:
At its heart, the Smart USB Thumb Drive brings together three key silicon devices:
- RP2040: Raspberry Pi’s dual-core ARM Cortex-M0+ microcontroller. You’ve seen it in the Pico. Here, it runs the show as the board’s main processor, connected to its own dedicated USB port. I use it to drive an OLED, and capture temperature and power draw data from on-board sensors. I have also included compact GPIO headers.
- GL3227E: A dedicated SD/eMMC-to-USB bridge controller. This chip makes the onboard eMMC storage appear as a standard USB mass storage device to any host computer.
- MTFC64GAPAL (153-ball TFBGA eMMC): 64GB of embedded MultiMediaCard storage, in a 0.5mm ball-pitch Ball Grid Array package. This chip is what put me on the path for this design.
The board also features a dual LM66100 ideal diode OR-ing power management topology, so the device stays powered seamlessly whether it’s drawing from the USB host or an alternative supply.
The idea for the project came when I decided I wanted to build something around BGA components. This is something I had not done in the past. The rest followed.
BGA (Ball Grid Array) components present several challenges that compound each other, especially on cost-constrained designs like a 2-layer board. These components are challenging primarily because their connections are hidden beneath the package, making routing escape, inspection, and rework extremely difficult. This forces designers into advanced techniques like via-in-pad, demands rigorous signal integrity practices, and requires the experience to distinguish genuine DRC violations from expected ones that are simply a normal consequence of fine-pitch BGA geometry.
As you can see, a lot to learn just from one chip on the board.
As I wasn’t satisfied with a simple USB storage device, I looked for ways to make the design more interesting, and I remembered someone in the community suggested a board based on the RP2040. So I thought this was a great opportunity to make the USB drive “smart”, and added a microcontroller on it. That brought along other requirements, like sensors, an OLED, and the dual USB setup.
The board has two USB Type-C connectors, and they serve different purposes. One connects the GL3227E storage controller so you can plug it into your computer and it mounts as a USB drive. The other connects the RP2040 for programming, serial debugging, or running your own USB device firmware or doing live telemetry on the drive’s operation status.
So, lot’s of challenges and learning there too.
But wait, there’s more 🙂
I could have routed this board on a four layer PCB comfortably (and I may still have to do that). But I went for a 2-layer design to force me to struggle with things such as proper placement, ground pours and return paths, protecting high-speed signals from noise, and other priorities that are much, much easier to do on four layers. I have already routed the board on 2-layers and it looks OK, but I’m still testing and evaluating to make sure I haven’t missed anything.
Another element I wanted to practice with was impedance-aware design but without paying for controlled impedance. Impedance-aware design means understanding and accounting for the impedance your trace geometry actually produces, rather than blindly targeting a nominal value or paying a manufacturer to control it for you. Instead of pretending you’ve hit 90Ω when your 2-layer stackup makes that impractical, you calculate what you’re actually getting, verify that the target interface’s signalling margins can tolerate the deviation, and document your reasoning. The goal is to get a functional, cost-effective design without the expense of controlled-impedance fabrication.
KiCad 10 is just around the corner, and I will record this course on it. As much as possible, I will try to use as many new KiCad 10 features as possible. I’m looking forward to use long anticipated features like the time-domain propagation delay tuning and DRC, which looks amazing. KiCad 10 will let us define delay profiles per layer and per via, so instead of manually converting matched trace lengths into timing estimates using a spreadsheet, the tool does it natively. This is a direct upgrade to the length-matching workflow I’ve used in previous project (and in this project in KiCad 9). With this feature I can show why length matching is really a proxy for delay matching, and what the actual numbers look like.
Another KiCad 10 feature I look forward to using is the Net Inspector time-domain details, which works in tandem with the time-domain propagation delay tuner. In KiCad 9, I already used the Net Inspector to verify the eMMC data track lengths; in KiCad 10 I can now also show delay breakdowns including track, via, and pad-to-die contributions.
And there’s more that I haven’t even thought about yet.
I will keep you informed about my progress, but of course feel free to ask me anything here.