KiCad 10 was released on March 20, 2026, the first day of autumn in the southern hemisphere. I find that timing fitting. Autumn is when things that have been growing all year reach maturity.
I have been teaching KiCad since version 4, and I wrote a comprehensive review of KiCad 6 back in early 2021 when it was still in development. A lot has happened in the five years since. KiCad 7, 8, and 9 each brought meaningful improvements, but version 10 feels like a step of a different kind. The feature list is long, and some of what landed here has been on the wishlist of professional engineers for years.
In this article I cover the most important new and improved features across the schematic editor, PCB editor, and general tooling. I also compare some capabilities against what commercial tools have offered, because context matters. And I include a few numbers that give a sense of the effort behind this release.
By the numbers
The KiCad 10 milestone tracked 500 work items, of which 494 were closed by release, 97% completion. The source repository received 7,609 unique commits during the development cycle, a notable increase over KiCad 9. 36 contributors participated in the milestone directly, supported by hundreds of developers, translators, library contributors, and documentation submitters.
The official libraries grew by 952 new symbols, 1,216 new footprints, and 386 new 3D models. Starting with this version, the 3D libraries ship STEP files only. VRML has been dropped. This reduces install size and gives better geometric accuracy. Over 78% of all footprints in the official library are now generated from data rather than drawn by hand.
Schematic editor
The most visible change in the schematic editor is hop-over display. Wire crossings that are not connected now show as arcs rather than a plain crossing line. This has been requested for years and the community celebrated it loudly when it landed. It makes complex schematics easier to read at a glance.
Local power symbols are also new. Until now, all power symbols in KiCad created a global net. If you placed a symbol labelled +3V3, that net existed everywhere in the design. Local power symbols scope a net to the current sheet only, which is useful when you want to reuse a sheet template without inadvertently connecting power rails across sheets.
The variant system is one of the bigger additions for anyone building products that ship in multiple configurations. Variants let you maintain a single schematic with multiple BOMs, different component values, or different fitted/not-fitted states, without duplicating the project. This is the kind of feature that professional organisations have needed from KiCad for a long time.
Grouping has arrived from the PCB editor. You can group symbols, wires, and labels in the schematic, and those groups can be automatically propagated to the PCB when you run Update PCB. If the group has a library link to a Design Block, that link carries through, keeping layout and schematic in sync.
Other improvements worth noting: live junction updates as you drag wires, a short-circuit warning when a drag would connect two different nets, multiple alternate body styles per symbol (extending the old De Morgan concept), drag-and-drop image import, and full expression evaluation in text strings. That last one lets you embed calculated values, dates, board area, and other dynamic content directly in board text.
PCB editor
The biggest PCB story in KiCad 10 is time-domain tuning, and it deserves an extended segment.
Time-domain tuning and Tuning Profiles
Until KiCad 10, length tuning in KiCad operated in physical units: millimetres or inches. For many designs that is sufficient, but at higher data rates it misses the point. Two traces of equal physical length on different layers, surrounded by different dielectric materials, will not exhibit the same propagation delay. It is delay, not distance, that determines whether a differential pair or a parallel bus meets its timing budget.
KiCad 10 introduces a complete time-domain tuning workflow built around Tuning Profiles, defined in Board Setup. A Tuning Profile specifies per-layer routing parameters including propagation delay. Profiles are assigned to netclasses, and the tuning tools switch automatically to time-domain mode when a netclass carries delay constraints. DRC rules can be written directly in picoseconds or femtoseconds. Pad-to-die delay is a first-class field in pad properties.
The propagation delay used by a Tuning Profile is not an arbitrary manual entry. The PCB Calculator derives it from the board stackup configuration and the trace geometry. Dielectric constants for the substrate materials are published by PCB fabricators (typically in the range of 3 to 5) and entered as part of the stackup definition; the calculator uses those values directly. For a single-ended trace, the user specifies the target impedance. For a differential pair, impedance and either track width or pair spacing are required, since specifying all three would over-constrain the problem. The propagation speed for each layer follows from the calculation.
The PCB Calculator covers microstrip, coplanar waveguide, coupled microstrip, stripline, and symmetric coupled stripline geometries. One practical limitation is worth understanding: the empirical formulae assume a uniform dielectric substrate. When a stripline sits between layers with differing material properties, the formulae introduce an approximation. For most standard FR4 and controlled-impedance stackups this is adequate in practice. For the most timing-sensitive designs, the recommended workflow is to use a fabricator-specified impedance-controlled stackup, run a dedicated external 2D field solver to derive precise parameters, and validate with a physical test coupon. The KiCad development team has indicated that integrated field-solver support is planned for a future release.
This release also resolves a long-standing inconsistency: the router, the status bar, the Net Inspector, and the DRC checker previously used different internal calculations, so the same trace could return different length values depending on which tool you asked. In KiCad 10 these are unified into a single calculation engine. If you have existing high-speed DRC rules with tight tolerances, verify them after upgrading, as the corrected values may surface violations that were previously masked by the inconsistency.
Note on pre-release builds: if you entered time-domain parameters in a KiCad 10 release candidate, those values do not transfer to the v10.0.0 release. Record them before opening your projects in the final release.
How does this compare to commercial tools? Altium Designer’s length tuning uses the Simbeor field solver to compute propagation delay automatically from the stackup, without requiring the user to specify trace impedance separately. KiCad 10’s approach uses empirical formulae with inputs derived from the same stackup data, which covers the core workflow and is adequate for most designs. The difference matters mainly at the extremes: very high data rates, non-standard stackups, or mixed-dielectric layer constructions where the uniform-substrate approximation degrades. That context aside, what KiCad 10 delivers is functional, free, and a genuine step change from tuning by millimetre.
Component Classes and dynamic assignment
Component Classes have been in KiCad for a while, but in version 10 they can be assigned dynamically in Board Setup using matching conditions: reference, footprint library, orientation, board side, field contents, schematic sheet name, or custom DRC expressions. This makes it practical to automatically classify SMD capacitors, high-speed signals, or power connectors into component classes without manually tagging each footprint.
Inner-layer objects in footprints
Footprints can now define objects, such as shapes and keepout areas, on specific inner copper layers. Previously, keepouts in footprints expanded to all inner layers, which was often too coarse. The new approach requires setting a custom stackup in the footprint properties. Without a custom stackup, the old behaviour is preserved, so existing footprints are not affected.
Design Blocks
Design Blocks, which let you save and reuse layout sections as library items, have been extended to the PCB editor. Groups in both editors now carry a “library link” connecting them to a source Design Block. You can apply the saved layout to a new instance of the block with a single command. Schematic groups transfer to the PCB along with their library links, keeping the two in sync.
DRC improvements
The DRC rule editor now has a graphical interface. Instead of writing custom rules by hand in a text file, you use a dialog with dropdowns, constraint panels, and object selectors. The rules it generates are fully compatible with the existing text-based rules language, so you can start with the GUI and switch to manual editing as needed.
A large number of DRC and ERC errors now have suggested fix actions. Dangling tracks, dangling vias, unannotated references, undefined netclasses, footprint mismatches, and more, all offer context menu actions that apply the fix directly.
Other PCB additions
Pin and gate swap with forward and back annotation between schematic and PCB. Native rounded rectangles. Hatched fills for graphic shapes. Barcodes as first-class objects: Code 39, Code 128, DataMatrix, QR, and MicroQR. 3D PDF export (requires Adobe Reader or Foxit; browser PDF viewers do not support the format). PCB “points”, which are zero-dimensional objects useful for IPC origin conventions and snap targets. Precise polygon point editing with live angle preview. Copper area reported in the status bar for selected items.
Symbol editor
The pin table now supports CSV export and import, which makes editing large components bearable. You can export the pin table to a spreadsheet, work with it there, and re-import. This also serves as a rough import mechanism for pin data converted from other sources.
A bulk field editor for symbols within a library is accessible from the right-click menu in the library tree. This saves a lot of tedious repetition when updating fields across a whole library.
Stacked pin number display now shows which pins share a location, which was a source of confusion in complex logic devices.
Features that close gaps with commercial tools
Three features in KiCad 10 are worth examining in the context of what commercial tools have offered.
Design variants. Altium Designer has included variant management since at least version 15 (around 2015). KiCad users have been working around this limitation for over a decade, maintaining multiple copies of projects or manually editing BOMs. KiCad 10 brings a native implementation. It is a first version and the documentation is still catching up, but the foundation is solid.
Pin and gate swap with back-annotation. This has been standard in professional EDA tools for a long time. KiCad 10 adds unconstrained pin/gate swap in both editors, with bidirectional annotation between schematic and PCB. Symbol pin swap is available but disabled by default, as it modifies local symbols to diverge from the library.
Time-domain tuning. As noted above, commercial tools such as Altium and Cadence have offered this for years. KiCad’s implementation is manual-entry-based rather than field-solver-based for now, but it covers the core workflow: per-layer propagation speeds, via delay overrides, pad-to-die delay, DRC in time units, and automatic tuning mode switching.
New importers
KiCad 10 can now import projects from Altium, CADSTAR, EasyEDA (JLCEDA) Standard and Pro, Allegro PCB, PADS PCB and schematic, and gEDA PCB and schematic. Combined with the existing Eagle importer, this means most of the major PCB formats in common use have a migration path into KiCad.
A short but useful list: customisable toolbars, undo/redo inside dialog boxes, lasso selection in both schematic and PCB editors, a true 1:1 screen-to-reality zoom level, 45-degree full-screen crosshairs, and a selection filter flash that tells you which filter is blocking a click when you can’t select an object. Symbols and footprints now load in the background at startup, so the chooser opens immediately rather than waiting on a loading bar. SpaceMouse support has been extended to Linux.
What’s next
The post-v10 forum thread confirms that KiCad 11 is targeting February 2027. The thread opened in January 2026 and development is just beginning, so there is nothing concrete to report yet. A 10.0.1 milestone is already open with initial items.
My take
KiCad 10 is the most substantial release in years. The time-domain tuning system alone justifies the version number; it changes how high-speed design is done in KiCad in a fundamental way. Variants and pin/gate swap address two of the most frequently cited gaps versus commercial tools.
The caveat I would offer is that several features are first versions. The variant system documentation is sparse. The time-domain tuning requires manual propagation speed entry. The graphical DRC rule editor is powerful but not yet as polished as the text-based rule system it complements. These are reasonable trade-offs for a community-driven open-source project, and the trajectory is clear.
If you have been teaching yourself PCB design with KiCad, or if you are considering whether KiCad can handle more demanding professional work, version 10 moves the answer in a positive direction. I will be updating both my KiCad Like a Pro and High-Speed PCB Design with KiCad courses to cover the most important new features.
If you are curious about how far KiCad has come, have a look at my KiCad 6 review from early 2021. Reading the two side by side gives a clear picture of how much has changed in five years.