PCB design - high-speed - GUIDE SERIES

Electrical Rules Check

Learn how to use KiCad’s Electrical Rules Check (ERC) to detect and correct schematic design errors before moving to PCB layout.

Before reading further, you can watch the companion video that demonstrates how to perform an ERC in KiCad for the LattePanda Mu Carrier schematic. The video shows how to interpret and fix ERC warnings and errors, ensuring your schematic is ready for layout.

Introduction

After completing the schematic wiring for the LattePanda Mu Carrier, the next crucial step is to verify the design using KiCad’s Electrical Rules Check (ERC).
The ERC tool analyzes your schematic to identify potential electrical problems such as unconnected pins, duplicated names, missing power connections, or misconfigured signal directions.
Even when working from a verified reference design, running ERC is essential to catch mistakes introduced during manual copying and wiring.

Running the ERC in KiCad

Open your schematic in KiCad and click the “Run Electrical Rules Checker” button.
KiCad will analyze all sheets in your project and generate a list of warnings and errors.
Warnings typically indicate potential issues that may not be critical, while errors often signify missing or incorrect connections that must be fixed.

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In most cases, you can double-click an entry in the ERC report to zoom directly to the affected symbol or net in the schematic.
For the LattePanda Mu Carrier project, the ERC report initially shows a mixture of valid warnings and genuine mistakes.

Understanding Warnings

Some warnings are benign and can safely be ignored once verified. For instance, you may see warnings about nets with multiple names.
In KiCad, if two nets share different names, the software will use one of them as the final name, which is usually harmless.
In this design, such warnings appear because differential pair nets (for example, USB or PCIe signal pairs) are labeled with additional identifiers to make them compatible with KiCad’s differential-pair routing tools.

Other harmless warnings arise when nets are duplicated for use across multiple hierarchical sheets—for instance, reusing the same USB data net for both the connector and an ESD protection device.

Common ERC Errors and How to Fix Them

KiCad may also report actual design errors that require attention. Below are common examples encountered during the LattePanda Mu Carrier schematic review and how they were resolved.

Common ERC Issues in the LattePanda Mu Carrier Design
Issue Type Cause Resolution
Missing Power Symbol A net connected to a power pin, such as +12V, lacks a defined power symbol. Add the appropriate power flag or symbol (for example, +12VA) to indicate a driven power net.
Input Pin Not Driven An input pin expects a signal from an output but is only connected to another input. If this matches the reference schematic, leave as is. Avoid editing symbol pin types, which may cause non-standard library behavior.
Power Output Not Detected Through Fuse KiCad cannot trace power connectivity through passive components like fuses. These warnings can be safely ignored; the schematic connection is still valid.
Duplicate Component Names Copied symbols retain identical reference designators (for example, two D9 diodes or two F2 fuses). Rename duplicates sequentially to maintain unique identifiers (for example, D5, D6, D7, etc.).
Unannotated Capacitors or Resistors Component copies were placed but not renamed (e.g., C40 duplicated in Ethernet and M.2 sheets). Assign correct designators following the reference schematic (e.g., C49–C54 for the M.2 section).

In most cases, ERC reports that involve missing voltage flags or duplicated names are straightforward to fix.
Warnings involving pin direction mismatches (for example, output-to-output or input-to-input) should be reviewed carefully.
If these match the official LattePanda schematic, they can be ignored to avoid altering standard library symbols.

Lessons Learned from ERC

Running the ERC is not just about eliminating all messages; it is about understanding which warnings matter and which do not.
During the verification of the LattePanda Mu Carrier schematic, most remaining warnings were intentional—such as input pins tied to inputs or power flowing through fuses.
The true errors were related to forgotten voltage symbols or duplicated component names, both easily corrected.

One common mistake was forgetting to rename components after copying sections of the schematic. This is easily prevented by annotating frequently during design and maintaining a consistent naming sequence across all sheets.

Final Verification

After addressing all critical issues, re-run the ERC.
A clean report should display no violations and only a few acceptable warnings.
At this stage, your schematic is verified and ready to proceed to PCB layout.
Running ERC regularly during schematic development helps catch problems early and prevents costly rework later.

Tip: ERC in KiCad is not a substitute for design experience. It cannot detect logical errors, such as miswired signal pairs or incorrect component footprints, but it is invaluable for verifying electrical consistency.

With this verification step complete, you are ready to move on to the next phase—translating your schematic into a physical board layout.

Ready for the next tutorial in this series? Here's the next one, or choose an alternative from the list of articles in the side bar. There's also lots of interesting article in our Blog. where you can read about off-grid communication technologies, electronics test equipment, course updates, and much more.

High-Speed PCB Design with KiCad

Learn to design a professional high-speed computer carrier board using KiCad, based on the LattePanda Mu Intel N100 compute module. You'll build a fully functional custom board that brings out USB, HDMI, Ethernet, GPIOs, and power interfaces.

Through hands-on practice, master multi-sheet schematic design, board layout, differential pair routing, and signal integrity. Learn essential concepts including stack-up configuration, impedance control, ESD protection, and grounding strategies, while using KiCad's advanced tools for hierarchical schematics and design rule verification.

Last Updated 11 months ago ago.

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