PCB Layers Count Considerations

Before reading further, you can watch the companion video, where I demonstrate how to complete the capacitor routing around the M.2 connectors on the LattePanda Mu Carrier and discuss how PCB layer count and routing strategy affect power and signal integrity.

Introduction

This section focuses on the power routing and decoupling capacitor placement for the M.2 Key M and Key E connectors on the LattePanda Mu Carrier.
At this stage, most high-speed signal interfaces have been routed, leaving power distribution and grounding as the next major tasks. Correct routing and capacitor distribution are essential to ensure stable power delivery and signal integrity in a dense, high-speed PCB design.

The Role of PCB Layer Count

Before adding copper pours or power planes, it’s crucial to understand the purpose of each PCB layer and plan how signals, power, and ground are distributed.

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For high-speed computer boards such as the LattePanda Mu Carrier, a four-layer PCB is a practical balance between cost, manufacturability, and performance.
A typical stack-up is:

A four-layer configuration allows power and ground planes to be located close together, improving signal integrity through reduced loop area and noise coupling.
If cost permits, six layers can further improve EMI performance and simplify dense routing, but for this course project, four layers are sufficient.

Capacitor Placement and Power Routing

Each M.2 connector—J15 and J16—has several pins carrying the 3.3 V power rail. These pins supply the connected M.2 devices (for example, an SSD or wireless module) and require local decoupling capacitors placed as close as possible to the pins.

The rule of thumb is to distribute capacitors evenly along the power pins. In this design, each M.2 connector has more 3.3 V pins than capacitors, so capacitors are split between the top and bottom sections of the connector: one set of bulk (10 µF) and local (100 nF) capacitors near each end.

This arrangement ensures that both ends of the power rail have stable local energy storage and short return paths to ground.

To interconnect these capacitors:

• Use wide copper traces (0.8–1.0 mm) for main 3.3 V rails on the inner power layer.
• Use vias with large diameters (≈0.4 mm) to transfer current from the surface pads to the internal power layer.
• Keep trace lengths short and direct, avoiding unnecessary bends that could increase impedance.

These techniques reduce voltage drop and help maintain a low impedance path for transient currents drawn by high-speed devices.

Decoupling and Ground Connection Strategy

Ground connections for all decoupling capacitors will later be tied to a solid ground copper pour on the inner layer.
At this stage, the ground plane should not yet be poured, as it’s better to complete the power and signal routing first.
Once all signal traces are finalized, copper pours can be added and stitched with vias for consistent grounding.

Each via connecting a capacitor to the ground plane should be as close as possible to the capacitor pad, minimizing inductive loop area and improving high-frequency performance.

Example Routing Strategy

When routing the 3.3 V nets:

1. Start from the power source (for example, the voltage regulator output).
2. Create a thick 3.3 V trace or plane on Inner Layer 2 or 3 that connects to all related pads on J15 and J16.
3. Place vias strategically between the pads and the plane.
4. Add the decoupling capacitors in parallel—each with its own short connection to both power and ground.

This approach matches the method used in the LattePanda reference design and provides a robust, low-noise power distribution network.

Moving Forward

With all capacitors placed and power routing completed, the next steps will include connecting all remaining GPIO nets and finalizing power-plane copper fills.
Once power and ground planes are added, you’ll be ready to analyze the board’s impedance characteristics and begin high-speed signal tuning in the layout phase.

By applying these PCB layer planning and capacitor placement strategies, you’ll achieve a reliable design foundation suitable for high-speed applications like the LattePanda Mu Carrier.

Ready for the next tutorial in this series? Here's the next one, or choose an alternative from the list of articles in the side bar. There's also lots of interesting article in our Blog. where you can read about off-grid communication technologies, electronics test equipment, course updates, and much more.