PCB design - high-speed - GUIDE SERIES
KiCad 9 Differential Pair Length Tuning Guide
Learn how to control and fine-tune the length of differential pairs in KiCad 9 to maintain precise signal timing and integrity.
Before reading further, you can watch the companion video for this guide. In it, I demonstrate how to set up, route, and length-tune differential pairs in KiCad 9 using real examples from the LattePanda Mu Carrier board. Watching the process will help you understand how the theoretical principles discussed here are applied in practice.
Introduction
Differential signals are essential for high-speed communication interfaces such as USB 3.0, HDMI, and PCIe, all of which are present on the LattePanda Mu Carrier. These signals are transmitted across two complementary traces—one carrying the positive version of the signal (TX+) and the other the negative version (TX–).
For differential signaling to work properly, these two traces must remain electrically balanced. This means they must have equal lengths, identical impedance, and consistent spacing along their entire route. When one trace is longer than the other, a timing skew occurs. Even a small mismatch—measured in fractions of a millimeter—can cause reflections, phase shifts, and signal degradation at high frequencies.
To prevent this, designers use a process called length tuning, which ensures both traces in a pair are matched to within a very tight tolerance.
Understanding Differential Pairs
A differential pair is composed of two signal traces carrying equal and opposite currents. The electromagnetic fields generated by the two signals cancel each other out, providing immunity to external noise and reducing emitted interference.
When properly routed, a differential pair behaves as a single transmission line with a well-defined impedance. Any difference in length between the two traces introduces skew, causing one signal to arrive slightly earlier than the other. At high speeds—such as those used in PCIe Gen 3 or USB 3.0—this can distort data transitions and impair system performance.
As a rule of thumb, the maximum allowable mismatch for high-speed interfaces should not exceed 0.05 mm between the two traces of a pair.
Defining Length Matching Rules in KiCad
KiCad 9 allows designers to set custom design rules for differential pairs. This ensures the software automatically checks for length mismatches and warns you when a pair exceeds the specified skew tolerance.
In this project, two key differential pair classes are used: one for 90 Ω pairs (USB 3.0 and Ethernet) and another for 100 Ω pairs (PCIe). The following custom rule constrains the maximum mismatch (skew) for each pair type:
| Net Class | Impedance | Maximum Allowed Skew | Purpose |
|---|---|---|---|
| 90-Ohm Differential | 90 Ω ±10% | 0.05 mm | Used for USB 3.0 and Ethernet pairs. |
| 100-Ohm Differential | 100 Ω ±10% | 0.05 mm | Used for PCIe and other high-speed clock pairs. |
By enforcing these constraints in Board Setup → Design Rules, KiCad ensures all routed differential pairs comply with the target impedance and length-matching requirements.
Performing Length Tuning in KiCad
After routing a differential pair, select it and press the “8” key or use the Length Tuning tool from the right-hand toolbar. KiCad will display the current lengths of both traces and guide you as you fine-tune them.
When one trace is shorter than the other, KiCad allows you to add meanders—small zigzag segments that slightly increase the length of the shorter trace. This technique equalizes the electrical path lengths of the two signals without affecting impedance or introducing excessive capacitance.
While tuning, keep these practices in mind:
- Always route the pair as a unit; never separate or detour one trace independently.
- Keep spacing consistent along the route to maintain constant differential impedance.
- Minimize the number of vias. If vias are necessary, ensure both traces use the same count and placement.
- Avoid switching layers when possible, as doing so can change impedance.
- After tuning, use the Length Skew Report to confirm all pairs meet the 0.05 mm tolerance.
Why Tight Matching Matters
The tolerance requirement of ±0.05 mm might seem excessive, but at multi-gigahertz frequencies even a few picoseconds of delay mismatch can cause significant degradation.
For example, in a USB 3.0 or PCIe Gen 3 signal running at 5 Gbps, one bit occupies only 0.2 nanoseconds. A 0.05 mm mismatch corresponds to roughly 0.3 picoseconds of delay, ensuring both signals arrive nearly simultaneously.
Tight length control prevents phase distortion and maintains common-mode noise rejection, which is one of the primary advantages of differential signaling.
Summary
Differential pair length tuning is one of the most important high-speed design techniques in KiCad. By maintaining matched trace lengths, consistent spacing, and controlled impedance, you preserve the timing and fidelity of high-speed signals.
With KiCad 9’s built-in rules and length-tuning tools, you can precisely adjust trace geometries and verify compliance automatically. These capabilities are critical for achieving professional-level results in designs like the LattePanda Mu Carrier, where interfaces such as PCIe, HDMI, and USB 3.0 depend on sub-millimeter precision.
In the next part of the project, we will apply these principles directly in the KiCad layout, tuning differential pairs across the board and confirming all skew values meet the strict design tolerance.
Ready for the next tutorial in this series? Here's the next one, or choose an alternative from the list of articles in the side bar. There's also lots of interesting article in our Blog. where you can read about off-grid communication technologies, electronics test equipment, course updates, and much more.
High-Speed PCB Design with KiCad
Learn to design a professional high-speed computer carrier board using KiCad, based on the LattePanda Mu Intel N100 compute module. You'll build a fully functional custom board that brings out USB, HDMI, Ethernet, GPIOs, and power interfaces.
Through hands-on practice, master multi-sheet schematic design, board layout, differential pair routing, and signal integrity. Learn essential concepts including stack-up configuration, impedance control, ESD protection, and grounding strategies, while using KiCad's advanced tools for hierarchical schematics and design rule verification.
Jump to another article
- 1 Introduction to high-speed PCB design
- 2 Learning high-speed design with LattePanda Mu reference design
- 3 A primer on high-speed PCB design
- 4 What are we designing in this course?
- 5 Setup the new KiCad project
- 6 Setup the schematic editor
- 7 Setup grid and avoid my mistakes
- 8 Create the hierarchical sheets
- 9 LattePanda Mu schematic sheet
- 10 Electrical Rules Check
- 11 PCB layers count considerations
- 12 Layout editor setup and basic configuration
- 13 Layout - Board outline and import components
- 14 Layout - Impedance and stack-up calculations
- 15 Routing preparation and plan
- 16 KiCad 9 Differential Pair Length Tuning Guide
- 17 Track length limits
- 18 DFM analysis and improvements
Last Updated 11 months ago ago.
We publish fresh content each week. Read how-to's on Arduino, ESP32, KiCad, Node-RED, drones and more. Listen to interviews. Learn about new tech with our comprehensive reviews. Get discount offers for our courses and books. Interact with our community. One email per week, no spam; unsubscribe at any time
