Layout – Impedance and Stack-Up Calculations

Before reading further, you can watch the companion videos that demonstrate how to calculate the impedance and configure the layer stack-up for the LattePanda Mu Carrier. The videos show how to use the NextPCB online calculator and apply its results to KiCad’s design rule editor.

Introduction

Impedance control is one of the most critical aspects of designing high-speed printed circuit boards (PCBs). It ensures that signals such as PCIe, USB 3.0, and Gigabit Ethernet maintain integrity as they travel across the board.

In this guide, you will learn how to calculate and apply controlled-impedance parameters using both manufacturer tools and KiCad’s layout editor. These steps form the foundation for high-speed routing and signal-quality assurance in the LattePanda Mu Carrier design.

Understanding the PCB Stack-Up

The LattePanda Mu Carrier is a four-layer board optimized for compactness, manufacturability, and controlled impedance. The stack-up follows a typical high-speed design arrangement:

This configuration minimizes electromagnetic interference, maintains stable impedance, and ensures a clear separation between high-speed signal layers and power distribution planes.

Using the Manufacturer’s Impedance Calculator

To achieve accurate results, designers must consider the exact manufacturing parameters. For this project, the NextPCB online impedance calculator was used.

Manufacturers provide such tools to model trace geometry based on dielectric properties, copper thickness, and spacing capabilities.

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By entering the substrate details (FR-4 dielectric constant, prepreg thickness, copper weight, etc.) and selecting the desired configuration—single-ended or differential pair—the calculator generates optimized trace widths and spacings.

The targets are as follows:

• 50 Ω for single-ended signals (e.g., GPIO, UART)
• 90 Ω for USB 3.0 and Ethernet differential pairs
• 100 Ω for PCIe differential pairs

The calculator ensures that the physical trace geometry meets these impedance values, balancing manufacturability with electrical performance.

Applying Calculated Values in KiCad

Once the impedance parameters are known, open Board Setup → Net Classes in KiCad and apply the following configurations:

Adjust Design Rules → Constraints to ensure that the minimum track width is at least 0.14 mm and the minimum clearance is around 0.10 mm. These values define the tightest manufacturing tolerances for high-speed routing.

Placement and Routing Strategy

With impedance control in place, the next step is to plan the physical layout.

The LattePanda Mu module is placed at the center of the board to serve as the primary interface hub. The M.2 Key M (for storage) and Key E (for Wi-Fi) connectors are located symmetrically on either side. The USB, Ethernet, and GPIO connectors are aligned along the outer edges for accessibility, while the power circuitry occupies the top section for thermal efficiency and simplified routing.

This balanced configuration keeps the differential pairs short, minimizes crosstalk, and supports consistent trace geometry throughout the layout.

Comparing with the Reference Design

The official LattePanda Mu Carrier design places the compute module in the top-right corner with both M.2 slots on one side.
In this custom board, the module is centered, and the slots are separated across both sides.

This choice improves physical access but results in slightly longer high-speed differential pairs. For instance:

• PCIe differential pairs measure approximately 83 mm.
• USB and HSIO pairs vary between 60 mm and 100 mm.

Although the PCIe specification recommends lengths below 75 mm, lengths up to 85 mm are acceptable for PCIe Gen 3 signals. The key is to maintain tight skew control—keeping the difference between the “+” and “–” traces below ±0.1 mm.

High-Speed Layout Guidelines

Several essential high-speed layout principles apply throughout the LattePanda Mu Carrier design:

• Keep differential pairs on the same layer to avoid via-induced skew.
• Maintain continuous reference planes beneath all high-speed traces.
• Minimize via count (preferably two per signal maximum).
• Ensure matched trace lengths within ±0.1 mm.
• Keep PCIe traces under 85 mm and USB 2.0 traces below 150 mm.

These rules conform to industry standards, including the Texas Instruments High-Speed Interface Layout Guidelines, and form the basis for reliable high-speed signal transmission.

Refinements and Future Adjustments

Testing of early prototypes indicated that moving the M.2 slots closer to the LattePanda connector would reduce differential pair lengths by approximately 10–15 mm. This change may be implemented in future iterations to further optimize signal integrity and compliance with high-speed timing constraints.

Finalizing the Design

After applying the impedance-controlled rules, trace widths, and clearances, the PCB is ready for high-speed routing.
Critical nets such as PCIe, USB 3.0, and Ethernet are routed first, ensuring differential pair tuning and minimal skew.
Low-speed signals and power traces are routed afterward with more relaxed constraints.

This process completes the impedance and stack-up configuration phase and establishes the foundation for a high-quality, manufacturable, and electrically stable LattePanda Mu Carrier board.

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