Routing Preparation and Plan

Before reading further, you can watch the companion video for this topic, where I explain how to organize the routing process based on the LattePanda Mu Carrier’s four-layer stack-up. The video demonstrates the rationale behind signal grouping, routing order, and grounding techniques.

Introduction

Routing is one of the most critical stages in PCB layout design. The objective is to guide signals efficiently across the layers while maintaining signal integrity, reducing electromagnetic interference (EMI), and ensuring manufacturability.

An offer from our sponsor

For the LattePanda Mu Carrier, the routing plan is based on a four-layer stack-up. This configuration provides an excellent balance between cost, performance, and design complexity. Understanding how to assign each layer’s purpose and how to route different signal types accordingly is key to achieving a high-quality board.

The Four-Layer Stack-Up

The carrier board follows a well-balanced four-layer stack-up:

This structure allows all critical signals to be routed directly over a solid ground reference, minimizing noise coupling and ensuring stable impedance.

Routing Order and Priorities

Routing follows a top-down order of signal importance, starting with the most sensitive and speed-critical nets:

1. High-Speed Differential Pairs:
   Begin with USB 3.0, HDMI (TMDS), Ethernet, PCIe, and any LVDS or clock pairs. These pairs must be tightly coupled, matched in length, and routed on the same layer—preferably the top layer (L1) or bottom layer (L4). Each pair should run over the solid ground plane on L2 to maintain a consistent return path.

2. High-Speed Single-Ended Signals:
   Next, route signals like SPI, fast I²C, and clock lines. Keep them short and ensure they have a continuous ground reference beneath. Avoid crossing power-plane splits on L3, as this interrupts the return current and increases EMI.

3. Medium-Speed Digital Signals:
   GPIOs, UART lines, interrupts, and chip selects fall into this category. These can be placed on the bottom layer (L4) to preserve space for more critical signals on the top layer.

4. Analog and Sensitive Traces:
   Use the top layer for analog signals to minimize noise. Keep them as short and direct as possible, and always route them over the solid ground plane (L2). Where necessary, use ground guard traces or physical separation from noisy digital circuits.

Maintaining Ground Continuity

A floating return path occurs when a signal trace does not have a continuous ground plane beneath it or crosses a split in the reference plane. This leads to increased impedance, noise, and electromagnetic emissions.

To prevent this, ensure that every signal has a solid reference plane. When routing on the bottom layer (L4), where the next internal layer (L3) is the power plane, add ground fills or strips above signal traces to provide a return path.

Ground stitching vias—vias connecting ground zones between different layers—are essential for keeping the ground potential consistent. These vias should be placed near high-speed differential pairs, signal transitions, and connectors to provide localized return current paths.

Power Distribution and Stitching

The power plane on L3 distributes voltage rails to various subsystems. Each power region is separated into split copper fills for different voltages. For low-current rails (like 3.3 V logic), wide traces or copper pours are sufficient. For higher-current components, such as LEDs or motor drivers, use large copper areas on L1 or L4 and tie them to the internal power plane with multiple vias.

Every power route should have a corresponding ground return path placed nearby. This reduces loop area and EMI emissions.

Ground stitching vias should connect:

• L2 (ground plane) to ground pours on L1 and L4.
• Ground fills around high-speed traces and near connectors.
• Areas with split power planes to maintain low impedance.

This approach ensures consistent current return paths and robust signal integrity.

Best Practices for Routing

When beginning the actual routing process, adhere to the following core guidelines:

• Keep differential pairs matched in length and spacing. Always route them together on a single layer.
• Avoid routing over split planes, as this disrupts return paths and increases noise.
• Minimize layer transitions, particularly for high-speed signals. If vias are necessary, place them near decoupling capacitors or ground stitching vias to maintain current continuity.
• Separate analog and digital sections of the board physically and electrically to prevent noise coupling.
• Use ground guard traces around sensitive analog or clock lines when appropriate.

These practices lead to a cleaner layout, improved manufacturability, and enhanced EMI performance.

Summary

This routing plan provides a structured approach for transitioning from schematic to physical layout. By prioritizing high-speed signals, ensuring consistent ground references, and following solid electromagnetic compatibility practices, you establish the foundation for a stable, reliable LattePanda Mu Carrier board.

In the next stage, the actual routing of differential pairs, single-ended traces, and power distribution networks will begin, applying the principles outlined in this plan.

Ready for the next tutorial in this series? Here's the next one, or choose an alternative from the list of articles in the side bar. There's also lots of interesting article in our Blog. where you can read about off-grid communication technologies, electronics test equipment, course updates, and much more.